Space-Native AI Inference Chip

Design for death.
Build to outlive.

Every AI accelerator in orbit today was designed for a data center on Earth. When a chip dies in space, it stays dead. This is the architecture of a chip designed from first principles around that constraint.

~0%
silent error rate
10–12yr
satellite lifetime
5–7nm
process node
RHBD
hardening approach
The Problem

Chips are the reason
space compute costs 4×

The analysis converges: launch cost is falling, cooling is tractable, power is abundant in orbit. The unsolved problem is chip mortality. Dead chips accumulate. Nobody comes to fix them.

40%
Overprovisioning
40% more hardware launched than needed just to cover expected failures.
5 yrs
Satellite useful life
Terrestrial DCs last 15 years. Orbital nodes retire at 5 due to dead chips.
20 min
To replace on Earth
In space that same failure is permanent for the satellite's life.
18×
Monthly capex vs Earth
SemiAnalysis traces this gap almost entirely to overprovisioning + short lifecycle.
Core Thesis

Trade FLOPS for lifetime.

“Trade 40% peak FLOPS for 10× better annual chip mortality.”

This trade is obviously wrong for Earth. It is obviously right for space. No existing chip has made it — because every existing chip was designed by an engineer optimizing for a benchmark, not for a satellite that cannot be serviced.

Design Pillars

Four decisions.
All wrong for Earth.

Each pillar makes a tradeoff that any Earth-focused chip designer would reject. In orbit, each is the right call. Click any to expand.

01⚡
Triple Mode Redundancy
Eliminate silent corruption
+3× area~0 silent errors
›
02🧠
Eliminate HBM
Replace the most vulnerable component
−50% bandwidth5× lower annual failure
›
03🔬
Deliberate Node Selection
5–7nm, not 2nm
−25% peak FLOPS3–4× better rad tolerance
›
04🔷
Graceful Degradation
Chiplet array with hot spares
−10% die efficiency10–12yr satellite life
›
TCO Impact

What 10× mortality improvement does.

The 18× monthly capital cost gap traces almost entirely to overprovisioning and short satellite lifecycle. This chip attacks both directly.

Hardware Overprovisioning
TODAY
40%
−35pp
THIS CHIP
5–10%
Satellite Useful Life
TODAY
5 years
+100%
THIS CHIP
10–12 years
Combined with eat-the-sun launch economics

Google's feasibility study puts cost-competitiveness at $200/kg to orbit. Starship targets $250/kg. The eat-the-sun orbital ring targets ~$50/kg via mass driver. At that launch cost, combined with this chip's mortality profile, orbital compute TCO crosses below terrestrial a decade ahead of any existing model's projection. No other team attacks both dominant cost drivers simultaneously.

Competitive Moat

Where everyone else stops.

PlayerHardeningFabUnit PriceVolume
Ramon.SpaceRHBP — Hardening by ProcessSpecialty gov fabs$10K–$100K/chipLow / gov
NVIDIA (Earth)Not hardenedTSMC 4nmCommercialMassive
→This ChipRHBD — Hardening by DesignTSMC 5–7nmCommercialHigh

Ramon.Space proves the market exists. They cannot serve it at scale — defense-process pricing locks them into government contracts. No commercial orbital compute operator can build a business on $100K chips. We fill that gap: commercial fab, commercial pricing, space-native design.

Roadmap

The credibility ladder.

Five rungs from zero to funded, with physical silicon in hand. No VC required to reach Rung 3.

✓
Architecture Document
Live on project site, downloadable as PDF
Week 1
2
Open-Source RTL
Gemmini fork + TMR module + chiplet degradation sim
Month 1–3
3
Real Silicon via Open MPW
Free shuttle, SkyWater 130nm — physical chips back in hand
Month 3–6
4
Academic Partner
Berkeley, MIT, or Georgia Tech for radiation validation
Month 2–4
5
Non-Dilutive Capital
DARPA ERI ($1–5M) or DoD SBIR Phase I ($150–300K)
Month 4–6
v0.1 Draft · June 2026 · All figures subject to revision